Conventional random access memory (RAM) operates by sending a charge through an appropriate column to activate a transistor at each bit in the column. A group of cells in the column is called a word. A single cell in the column is typically referred to as a bit.
In many modern computing architectures, the memory supports what is commonly termed a “wide word,” sometimes 16, 32, 64, or even 128-bits wide. Also, in modern computing architectures, logical operations on words often include writing only a portion of the wide word. To accomplish this, a write mask mechanism is typically employed to mask writes, thus writing only unmasked bits to the memory wide word without affecting bits at masked positions.
In use, values in the memory cells corresponding to the masked bits must remain stable, and not significantly lose charge or logic value. Measurement of this characteristic is known as cell stability. It is well known that higher current (and hence power) being applied to the write bitlines does indeed enhance such cell stability, however at the cost of power consumption.
As semiconductor feature sizes decrease, attempts to address the attendant cell stability challenges have included using differential bitlines, and also have included performing write masking on those bitlines, either by forcing a ‘11’ on the differential pair, or by floating the shared bitlines. Both of those techniques have cell stability and power consumption characteristics that leave room for improvement.
There is thus a need for addressing these and/or other issues associated with the prior art.